The clock-recovery circuitry is in principle a form of PLL with a special type of digital phase comparator. The comparator allows for VCO phase adjustment only when high-to-low or low-to-high ...

Cost: In certain situations, a simple analog multiplier circuit is cheaper to implement than a complex digital multiplier, especially for low-precision applications.

A PLL is overkill for some applications, however, especially if the input frequency needs only to be doubled. For those cases a simpler approach”such as the circuit in Figure 1″ will do the job just ...

A simple comparator-based DTC gain calibration technique is used to reduce the dependency on multi-bit time-to-digital converters (TDCs). This helps minimize clock duty cycle distortion and improves ...

The Signetics circuit was like this PLL AM demodulator from a Texas Instrument’s data sheet By using a four-quadrant multiplier for the audio demodulator, both positive and negative parts of the AM ...

Circuits, Inc. (TCI), a leading provider of analog and mixed-signal intellectual property (IP) for the semiconductor, systems and electronics industries announced today the availability of a new line ...

Every communications product and system needs a highly stable and reliable clock. Stability and reliability both are harder to achieve at higher clock frequencies--especially over 100 MHz. While ...

TLSI today announced a very-low-jitter, high-frequency PLL clock-multiplier IC, the T98553, that is designed to replace high-cost crystal oscillators for use in serial data communications market.

In operation, these three pairs of readings are used to electronically compensate for remaining temperature effects (see graph left) by an on-board polynomial predictive algorithm that corrects the ...