Zero defect in semiconductor packaging is key especially for high demanding reliability applications (automotive, spatial...) combined with high performance technologies (Silicon ultra lowK wafers ...

In flip-chip packages, the coefficient of thermal expansion (CTE) mismatch between the chip and the substrate is the root cause for reliability issues such as excessive warpage, low-k dielectric layer ...

The Chinese Academy of Sciences unveiled a fully automated processor chip design system, claiming the potential to accelerate semiconductor development and replace human programmers. Micron Technology ...