Writing an SDRAM controller from scratch isn’t for the fainthearted – first of all you really have to know how SDRAM works (RAS, CAS, precharges, refresh cycles), and because of the high speed ...

This paper deals with reusability issues in the development of a double data rate (DDR) SDRAM controller module for FPGA-based systems. The development of integrated systems-on-a-chip (SoC) is based ...

The recently introduced DDR3 SDRAM technology paves the way to higher data rates (from 800 Mbps to 1600 Mbps) and provides higher performance for many systems that depend on data, video, or packet ...

Partnering with Altera, the company has introduced a double-data rate (DDR) SDRAM controller capable of performing control functions at up to 266 MHz when implemented into the company's EP20K400E ...

The DDR SDRAM controller logic must also facilitate the refresh requirements for the DRAMs. Arbitrating between a latency intolerant command and an overdue refresh requirement requires complex ...

We're designing an SDRAM controller as part of an EE project and we can't seem to get the data mask function (i.e. DQM pins) to work properly with our 32MB PC100 144-pin SODIMM. <BR><BR>We are ...

The DDR SDRAM controller IP core for LatticeECP and LatticeEC FPGA families features programmable burst lengths of 2, 4, or 8; CAS latency of two or three cycles; intelligent bank management; as many ...

A controller is required to provide proper commands for SDRAM initialization, read/write accesses and memory refresh. This paper describes the design of a synthesizable SDRAM controller IP core ...

Billed an IoT Maker Board, the tiny board sports a Intel (formerly Altera) MAX10 device with 8,000 logic elements, a USB programming interface onboard, 8 MB of SDRAM, and both PMOD and Arduino MKR ...

Now-a-days, DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory) has become the most popular class of memory used in computers due to its high speed, burst access and pipeline ...

The company has announced what it is calling the industry’s first 533-Mb/s DDR2 SDRAM controller IP core supporting the LatticeECP2/ECP2M low-cost FPGA families, and the high-end LatticeSC FPGA ...